An Inside Look at the LAVA Parallel-PCI

19th Monday, 2011  |  Engineering News, Life at LAVA  |  no comments

Recently we had a customer inquiry about the internals of one of our parallel port cards. To answer, we had to take a refresher course in what our design contained. That process led us to think: why not let interested technically-minded people see what’s inside the LAVA parallel EPP port design? We decided we would.

So here’s something never before seen outside of LAVA’s engineering department: the schematic design of our PCI-to-EPP parallel port bridge circuit. It’s the basis for LAVA’s Parallel-PCI. This design revolutionized PCI bus expansion in the industry, as it was the first implementation of a parallel port to take advantage of the speed of the PCI bus. Early versions of LAVA Parallel-PCI cards using this design wrote the circuit into a Xilinx FPGA (Field Programmable Gate Array); fairly soon afterwards it was incorporated into the first version of our LAVA ASIC, the application-specific integrated circuit that is the backbone engineering of LAVA PCI-bus serial and parallel cards to this day.

Xilinx and ASIC chips

Xilinx and ASIC chips

The design shown in this PDF is the newest production version of this design, and it’s what you get when you buy a Parallel-PCI, Parallel-PCI/LP, or Dual Parallel-PCI. It’s also the parallel port portion of the SP-PCI, or 2SP-PCI serial-parallel combo cards. All of these cards use this EPP parallel circuit.

The LAVA ASIC also contains circuits for serial ports, but that is a story for another day.